The invention relates to an epitaxial structure that contains optoelectronic devices embedded in Si, such that the entire wafer can be processed using traditional Si CMOS tools to create a true monolithic optoelectronic integrated circuit (OEIC).
It has been a long-standing desire of the microelectronics and telecommunications industries to combine optoelectronic components with Si circuitry. Adding optoelectronic functionality to standard Si integrated circuits (ICs) would enable a tremendous range of new applications and devices, such as on-chip optical communication (enabling optical clock timing for high speed processors), inter-chip optical communication links (optical interconnects), and more efficient and compact optical transceivers for data communications and telecommunications.
Although hybrid integration of optical components with Si ICs provides a possible solution, this is not the preferred solution. True monolithic integration of optoelectronics with Si circuitry is far superior to hybrid integration for several reasons. Monolithic integration yields more compact devices (and therefore higher device integration densities); lower packaging costs since wire bonds or flip-chip bonds between the optoelectronic component and Si IC necessary in hybrid integration schemes are eliminated; lower processing costs since the entire device can be processed using standard Si CMOS techniques; and improved device characteristics in applications where hybrid integration yields undesirable electrical parasitics.
It is therefore desirable to create a truly monolithic structure containing both optoelectronic functionality and Si CMOS circuitry. However, an intrinsic problem with integrating optoelectronic functionality into Si chips is that Si itself is not a good optoelectronic material as it neither emits nor detects light efficiently. Therefore, the optically active material integrated with the Si CMOS circuitry must be something other than Si, such as Ge, SiGe, GaAs, InP, AlGaAs, InGaAs, InGaAsP, or any other optically active group IV or III-V semiconductor material. Due to the large lattice mismatch and thermal expansion coefficient mismatch between these materials and Si, monolithically integrated devices created until now have been performance limited by the resulting crystalline defects (specifically threading dislocations) from epitaxy. However, recent progress in defect filtering schemes, such as graded buffer layers or selective epitaxial growth and epitaxial lateral overgrowth, has overcome this problem and enabled the creation of lattice-mismatched epitaxial layers of suitable quality for optoelectronic devices, such as photodetectors, light emitting diodes (LEDs), and lasers.
A major limitation of monolithic optoelectronic integrated circuits created until now has been the requirement that all Si CMOS processing steps be fully completed before integration of the optically active material. This requirement has existed because Si CMOS processing tools cannot be exposed to any other materials due to contamination concerns.
It is therefore an object of the invention to provide an epitaxial structure in which an optically active semiconductor devices embedded within Si such that the entire wafer can be processed using traditional Si CMOS tools to yield a true monolithic optoelectronic integrated circuit.
The invention provides a structure in which the optically active layer is embedded in a Si wafer, such that the outermost epitaxial layer exposed to the CMOS processing equipment is always Si (or another CMOS-compatible material such as SiO2). Since the optoelectronic layer is completely surrounded by Si, the wafer is fully compatible with standard Si CMOS manufacturing. Therefore, all of the manufacturing and cost benefits associated with Si CMOS processing are fully realized by the invention.
It is important to note that embedding the optoelectronic layer in Si does not prevent transmission of optical signals between the OEIC and an external waveguide (such as an optical fiber) or free space. Specifically, for wavelengths of light longer than the bandgap of Si (1.1 xcexcm), Si is completely transparent and therefore optical signals can be transmitted between the embedded optoelectronic layer and an external waveguide using either normal incidence (through the Si substrate or top Si cap layer) or in-plane incidence (edge coupling). This provides tremendous flexibility in designing an OEIC used for the typical telecommunications wavelengths of 1.3 and 1.55 xcexcm. Additionally, even wavelengths shorter than the bandgap of Si can be coupled in and out of the embedded optoelectronic layer. This is because the top Si cap layer can be made thin enough that it is only minimally absorbing at other commonly used wavelengths, such as 980 or 850 nm. Alternatively, edge coupling could be used for these wavelengths. This flexibility facilitates design of complex system-on-a-chip structures where multiple wavelengths and/or multiple optical in/out connections are required.